Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

• Published in: IEEE transactions on electron devices Vol. 64; no. 11; pp. 4587 - 4593
• Main Authors: Witters, L., Arimura, H., Sebaai, F., Hikavyy, A., Milenin, A. P., Loo, R., De Keersgieter, A., Eneman, G., Schram, T., Wostyn, K., Devriendt, K., Schulze, A., Lieten, R., Bilodeau, S., Cooper, E., Storck, P., Chiu, E., Vrancken, C., Favia, P., Vancoille, E., Mitard, J., Langer, R., Opdebeeck, A., Holsteyns, F., Waldron, N., Barla, K., De Heyn, V., Mocuta, D., Collaert, N.
• Format: Journal Article
• Language: English
• Published: IEEE 01.11.2017
• Subjects: finFET; FinFETs; Gallium arsenide; gate-all-around (GAA); ground-plane (GP) doping; high-pressure anneal; Logic gates; nanowire (NWs); Nanowires; Silicon germanium; Strain; strain relaxed buffer (SRB); strained germanium
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2017.2756671

Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs to increase the drive per footprint. The demonstrated short-channel devices have round Ge NWs with 9-nm diameter and are the Ge GAA devices with the smallest channel and gate dimensions (L G = 40 nm) published to date. Electrostatics and off-state leakage are maintained down to the shortest gate lengths studied, showing drain-induced barrier lowering of 30 mV/V and sub20 nA/μm I off at V DD = -0.5 V and L G = 40 nm. The short-channel device subthreshold slope SS and performance can be further improved by use of high-pressure annealing in hydrogen, yielding the best SSLIN and SSSAT of 71 and 76 mV/dec reported so far for any L G = 40-nm Ge pMOS channel device.