A tree-matching chip

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 7; no. 2; pp. 277 - 280
• Main Authors: Krishna, V., Ranganathan, N., Ejnioui, A.
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.06.1999; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Artificial intelligence; Chips (electronics); Computational modeling; Computer architecture; Computer science; control theory; systems; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Hardware; Information, signal and communications theory; Integrated circuits; Iterative algorithms; Machine vision; Matching; Mathematical analysis; Mathematical models; Object recognition; Pattern matching; Pattern recognition; Pattern recognition. Digital image processing. Computational geometry; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal processing; Systolic arrays; Telecommunications and information theory; Trees; Very large scale integration; Virtual prototyping; Parallel algorithm; VLSI circuit; Theoretical study; Tree structure; Pattern recognition; Chip; Systolic network
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/92.766755

Tree matching is an important problem used for three-dimensional object recognition in image understanding and vision systems. The objective of tree matching is to find the set of nodes at which a pattern tree matches a subject tree. In this paper, we describe the design and implementation of a very large scale integration (VLSI) chip for tree pattern matching. The architecture is based on an iterative algorithm that is mapped to a systolic array computational model and takes O(t(n+a)) time to profess a subject of size n using a processors where a is the length of the largest substring in the pattern and t is the number of substrings in the pattern. The variables and nonvariables of the pattern tree are processed separately, which simplifies the hardware in each processing element. The proposed partitioning strategy is independent of the problem size and allows larger strings to be processed based on the array size. A prototype CMOS VLSI chip has been designed using the Cadence design tools and the simulation results indicate that it will operate at 33.3 MHz.