Asymmetric Aging: Introduction and Solution for Power-Managed Mixed-Signal SoCs

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 22; no. 3; pp. 691 - 695
• Main Authors: Jain, Palkesh, Cano, Frank, Pudi, Bapana, Arvind, N. V.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Aging; asymmetric aging; Asymmetry; Circuits; clock tree; Clocks; CMOS; Degradation; Design engineering; Guidelines; Logic gates; Management; Negative bias temperature instability; negative bias temperature instability (NBTI); skew; Stress; Thermal variables control; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2013.2251022

A detailed introduction to the problem of asymmetric aging of mixed signal CMOS circuits is given in this paper, with special focus on clock skew, pulse width, and aspects of burn-in. A comprehensive look into the origin and aggravation of the problem due to power management techniques is presented. Additionally, various asymmetric aging analyses and management techniques, including conventional timing analysis frameworks, are shared. For the first time, problem formulation and desensitization schemes in a statistical framework are presented. Subsequently, design guidelines are shared that can be applied on production clock designs to significantly alleviate the asymmetric aging problem. Several of these techniques must be applied to advanced production designs to enable higher performance and integrity.