Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 57; no. 8; pp. 607 - 611
• Main Authors: U-Fat Chio, He-Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Martins, R P, Maloberti, Franco
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog-to-digital converter (ADC); Architecture; Circuits; CMOS; CMOS technology; Cost function; Design engineering; Digital; digital error correction (DEC); Error correction; Flash ADC; Laboratories; Low voltage; Noise levels; Optimization; SAR ADC; Semiconductor device measurement; Silicon compounds; subranging ADC; Synthetic aperture radar; Very large scale integration
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2010.2050937

This brief presents the architectural concept of an optimal subranging ADC, obtained with the cascade of a Flash and a SAR, which is also explored through its practical design and experimental confirmation. The solution doubles the optimal speed of operation of the SAR ADCs at the relative low power cost of a low-resolution Flash. The digital correction method and a capacitor-based DAC ensure nondemanding requirements for the Flash. The effectiveness of the architecture is verified in a 90-nm CMOS chip whose active core area is 0.64 mm 2 . The ADC obtains a peak SNDR of 51.8 dB and SFDR of 63.4 dB at 90 MS/s consuming 13.5 mW from a 0.9-V supply. Measured DNL and INL are 0.87 LSB and 1.55 LSB, respectively.