A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 24; no. 7; pp. 2570 - 2579
• Main Authors: Kim, Young-Hwa, Cho, SeongHwan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital; analog-to-digital converter (ADC); Calibration; CMOS integrated circuits; comparator-based switched capacitor; Current sources; Delays; Gain; gain calibration; High speed; nonlinear calibration; Nonlinearity; offset calibration; Offsets; Permissible error; pipeline; Pipelines; Resistors; Very large scale integration; zero-crossing based; zero-crossing-based circuit (ZCBC); pipeline; comparator-based switched capacitor; nonlinear calibration; Analog to digital; offset calibration; zero-crossing-based circuit (ZCBC); analog-to-digital converter (ADC); calibration; gain calibration; zero-crossing based
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2015.2508564

A zero-crossing-based circuit (ZCBC) is a promising technique for low-power high-resolution pipeline analog-to-digital converters (ADCs). Unfortunately, operating ZCBC ADCs at high speeds near 1 GS/s is quite challenging due to the delay of the zero-crossing detector that introduces nonlinear gain and offset errors. To solve nonlinearity, we propose a ZCBC pipeline ADC that employs a passive resistor as a current source. Due to its inherent linearity, the resistor-based ZCBC eliminates the input dependency of the interstage gain and offset errors, allowing a simple calibration. Furthermore, a background offset calibration scheme is proposed to cope with the large offset that results from high-speed operation. A prototype ADC implemented in 65-nm CMOS achieves an SNDR/SFDR of 47.26/62.64 dB at 1 GS/s while consuming 46.52 mW from 1 V supply.