A 0.5 V 1.28-MS/s 4.68-fJ/Conversion-Step SAR ADC With Energy-Efficient DAC and Trilevel Switching Scheme
This paper describes a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient trilevel alternate switching capacitive digital-to-analog converter (CDAC). The switching scheme of this CDAC preserves the features of the asymmetric-switching CDAC. By n...
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Published in | IEEE transactions on very large scale integration (VLSI) systems Vol. 24; no. 4; pp. 1441 - 1449 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
New York
IEEE
01.04.2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | This paper describes a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient trilevel alternate switching capacitive digital-to-analog converter (CDAC). The switching scheme of this CDAC preserves the features of the asymmetric-switching CDAC. By narrowing and smoothing the dynamic variation of DAC voltage, the switching scheme diminishes the dynamic offset effect induced by the asymmetric-switching CDAC. The CDAC reduces the capacitor requirement by almost fourfold and improves the average switching energy efficiency by almost 86.5% when compared with the conventional switching CDACs. This SAR ADC was implemented using the 90-nm CMOS technology, and its measured performances were as follows: 1) spurious free dynamic range of 56.98 dB; 2) signal-to-noise-and-distortion ratio of 68.79 dB; and 3) power dissipation of 3.45 μW at an operation of 0.5 V and 1.28 MS/s. The ADC achieves a figure-of-merit of 4.68-fJ/conversion-step. |
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Bibliography: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
ISSN: | 1063-8210 1557-9999 |
DOI: | 10.1109/TVLSI.2015.2448575 |