An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors

• Published in: IEEE journal of solid-state circuits Vol. 47; no. 11; pp. 2627 - 2642
• Main Authors: Loke, A. L. S., Doyle, B. A., Maheshwari, S. K., Fischette, D. M., Wang, C. L., Tin Tin Wee, Fang, E. S.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.11.2012; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Bandwidth; Bang-bang PLL; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); clean-up PLL; Clocks; CMOS integrated circuits; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; forwarded clock; HyperTransport (HT); Integrated circuits; Integrated circuits by function (including memories and processors); Jitter; jitter tracking; low power; Oscillators, resonators, synthetizers; Phase locked loops; Program processors; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Servers; source synchronous; Voltage-controlled oscillators; wireline transceivers; Processor; Jitter; Driver; Clock; jitter tracking; source synchronous; Implementation; Transceiver; Ring oscillator; Silicon on insulator technology; Long channel; FIFO system; Energetic efficiency; Complementary MOS technology; Electronic packaging; Phase error; CMOS integrated circuits; Root mean square value; Bang―bang PLL; High performance; Power circuit; Receiver; Power electronics; Phase locked loop; Phase detector; forwarded clock; Integrated circuit; low power; Compatibility; High frequency; HyperTransport (HT); clean-up PLL; wireline transceivers
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2012.2211697

We present an 8.0-Gb/s HyperTransport source-synchronous I/O integrated in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design capping at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels by incorporating several jitter- and power-reduction enhancements. First, a high-bandwidth digital clean-up PLL is introduced to attenuate high-frequency jitter in the received forwarded clock before the data is sampled. This PLL achieves a highly programmable jitter bandwidth of 20-296 MHz (measured with 0.2 UI pp input jitter) and 0.90-1.50 ps output rms jitter by implementing an extended bang-bang phase detector for additional phase-error magnitude information and flexible bang-bang control of a current-starved ring-based oscillator. Second, several power-hungry circuits, namely the transmitter input FIFO and output driver as well as the receiver deserializer, are redesigned for 8.0-Gb/s operation to maintain thermal compatibility with the existing 45-nm socket package. The fabricated 20-lane I/O consumes 1.70 W at 8.0 Gb/s with an energy efficiency of 11.8 pJ/bit. This reflects a 4.9% increase in HyperTransport power consumption and only 0.3% increase in total processor target power relative to 45-nm operation at 6.4 Gb/s.