A Frequency Model of a Continuously Driven Clocked CMOS Comparator

A frequency model of a continuously driven clocked CMOS comparator with the effect of the input signal during regeneration is presented. The model utilizes a small-signal linear model derived from the theoretical analysis of the comparison error caused by the transition from the tracking mode to the...

Full description

Saved in:
Bibliographic Details
Published inIEEE transactions on circuits and systems. II, Express briefs Vol. 57; no. 12; pp. 956 - 960
Main Authors Okura, Shunsuke, Shibata, Hajime, Okura, Tetsuro, Ido, Toru, Taniguchi, Kenji
Format Journal Article
LanguageEnglish
Published New York IEEE 01.12.2010
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Circuits
Clocked comparator
Clocks
CMOS
CMOS integrated circuits
Comparators
Electric potential
Frequency response
High speed
metastability
Regeneration
Semiconductor device modeling
Simulation
Tracking
Transfer functions
Voltage
Online AccessGet full text

Cover

More Information
Summary:A frequency model of a continuously driven clocked CMOS comparator with the effect of the input signal during regeneration is presented. The model utilizes a small-signal linear model derived from the theoretical analysis of the comparison error caused by the transition from the tracking mode to the regeneration mode. The comparison error voltage is a function of input signal frequency and is represented with the transfer function. The correctness of the model is assured by several transistor-level simulation results. The model provides a valuable insight for the design of high-speed comparators.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2010.2087972