Channel Models for Multi-Level Cell Flash Memories Based on Empirical Error Analysis

• Published in: IEEE transactions on communications Vol. 64; no. 8; pp. 3169 - 3181
• Main Authors: Taranalli, Veeresh, Uchikawa, Hironori, Siegel, Paul H.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analytical models; Asymmetry; Bit error rate; channel model; Channel models; Channels; Cycles; Direct selling; Empirical analysis; Error analysis; error correcting codes; Error correction codes; Errors; Estimation; Flash memories; Flash memory; Flash memory (computers); multi-level cell; P/E cycling; Simulation; Statistical tests
• ISSN: 0090-6778; 1558-0857
• DOI: 10.1109/TCOMM.2016.2584602

We propose binary discrete parametric channel models for multi-level cell (MLC) flash memories that provide accurate error-correcting code (ECC) performance estimation by modeling the empirically observed error characteristics under program/erase cycling stress. Through a detailed empirical error characterization of 1X-nm and 2Y-nm MLC flash memory chips from two different vendors, we observe and characterize the overdispersion phenomenon in the number of bit errors per ECC frame. A well-studied channel model, such as the binary asymmetric channel model, is unable to provide accurate ECC performance estimation. Hence, we propose a channel model based on the beta-binomial probability distribution [2-beta-binomial (2-BBM) channel model], which is a good fit for the overdispersed empirical error characteristics, and show through statistical tests and simulation results for BCH, low density parity check, and polar codes, that the 2-BBM channel model provides accurate ECC performance estimation in MLC flash memories.