FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping

Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension o...

Full description

Saved in:
Bibliographic Details
Published inIntegration (Amsterdam) Vol. 68; pp. 108 - 121
Main Authors Soliman, Shady, Jaela, Mohammed A., Abotaleb, Abdelrhman M., Hassan, Youssef, Abdelghany, Mohamed A., Abdel-Hamid, Amr T., Salama, Khaled N., Mostafa, Hassan
Format Journal Article
LanguageEnglish
Published Amsterdam Elsevier B.V 01.09.2019
Elsevier BV
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1). •A new dimension of security for constrained IoT devices using the concept of algorithm hopping.•Dynamic Partial Reconfiguration technology is used for switching between lightweight ciphers.•Area and Power reduction using the DPR technique with more security.
ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2019.06.004