VLSI based Lossless ECG Compression Algorithm Implementation for Low Power Devices

• Published in: Journal of physics. Conference series Vol. 1964; no. 6; pp. 62073 - 62078
• Main Authors: Kuppusamy, P G, Sureshkumar, R, Yuvaraj, S A, Dilliraj, E
• Format: Journal Article
• Language: English
• Published: Bristol IOP Publishing 01.07.2021
• Subjects: Algorithms; Channel capacity; Compression; Data compression; ECG; EEG; Electrocardiography; Electronic devices; Fibrillation; Functions (mathematics); Gate counting; Integrated circuits; Lossless equipment; Low power; Mathematical functions
• ISSN: 1742-6588; 1742-6596
• DOI: 10.1088/1742-6596/1964/6/062073

The research study presents a VLSI design of an effective electrocardiogram data encoding lossless data compression scheme to conserve disk system to minimize channel capacity. As the data compression can save disc space, reduce transfer time, and seized this ability by introducing a memory-less architecture when operating in VLSI at a high data rate. There are two components of the ECG classification technique: an adaptive frequency-domain methodology and bandwidth. An accurate and reduced VLSI compressed algorithm design has been introduced. The current VLSI architecture uses a few more procedures to substitute for the various mathematical functions to enhance performance and implemented the VLSI’s architecture to the MIT-BIH atrial fibrillation repository capable of achieving a 2.62 lossless bit compression rate. Also, the VLSI structure uses a gate count of 5.1 K.