Analog-binary CCD correlator: a VLSI signal processor

Designs of key sections of a 512-stage correlator are discussed. The chip measures nearly 400 by 300 mils and contains all circuits necessary to accept and store a reference code and compare it to a signal. In addition, it contains many support circuits including the clock logic and drivers, code lo...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 14; no. 2; pp. 518 - 525
Main Authors Gandolfo, D.A., Tower, J.R., Pridgen, J.I., Munroe, S.C.
Format Journal Article
LanguageEnglish
Published IEEE 01.04.1979
Subjects
Charge coupled devices
Clocks
Correlators
Driver circuits
Harmonic distortion
Logic circuits
Process design
Semiconductor device measurement
Signal processing
Very large scale integration
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Summary:Designs of key sections of a 512-stage correlator are discussed. The chip measures nearly 400 by 300 mils and contains all circuits necessary to accept and store a reference code and compare it to a signal. In addition, it contains many support circuits including the clock logic and drivers, code load logic, and TTL-to-MOS converters. Design of the floating-gate tap structure minimizes code-dependent bias, harmonic distortion, and tap-to-tap nonuniformity, while holding power dissipation to 1 mW per tap. Electron-beam lithography was used to produce photomasks with low defect density and tight dimensional tolerances over the array.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1979.1051205