Bandwidth optimization of flash memories with the RGP technique

A simple expression for the number of bits that can be programmed per unit time (bandwidth or BW) in flash memories with the ramped gate programming (RGP) technique is used to optimize memory BW and derive design curves. Preliminary experimental results obtained with common-ground NOR flash memory a...

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Bibliographic Details
Published inIEEE transactions on electron devices Vol. 48; no. 8; pp. 1737 - 1740
Main Authors Versari, R., Esseni, D., Falavigna, G., Lanzoni, M., Ricco, B.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.08.2001
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Arrays
Bandwidth
Circuit optimization
Devices
Flash memory (computers)
Gates
Optimization
Programming
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Summary:A simple expression for the number of bits that can be programmed per unit time (bandwidth or BW) in flash memories with the ramped gate programming (RGP) technique is used to optimize memory BW and derive design curves. Preliminary experimental results obtained with common-ground NOR flash memory arrays realized with 0.25 /spl mu/m technology show that memory BW can: (1) exceed of 10 Mb/s with optimized cell programming and (2) be negatively affected by device scaling.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
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ISSN:0018-9383
1557-9646
DOI:10.1109/16.936696