Design and Stability Analysis of a Low-Voltage Subharmonic Cascode FET Mixer

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 59; no. 3; pp. 153 - 157
• Main Authors: Hu Zijie, Mouthaan, K.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2012; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Admittance; cascode FET; class-B biasing; Conversion; Electric potential; FETs; Harmonic analysis; Integrated circuits; large-signal stability analysis; Mixers; Noise levels; Oscillations; Oscillators; parametric oscillations; Radio frequency; Stability analysis; subharmonic mixer (SHM); Voltage
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2012.2184379

A novel biasing scheme to realize a low-voltage subharmonic cascode FET mixer is presented. The proposed biasing requires a low supply voltage and effectively facilitates the generation of the second harmonic of the local oscillator (LO) signal for subharmonic mixing. Hence, the proposed subharmonic mixer (SHM) exhibits competitive performance at a lower supply voltage compared with conventional SHMs. Additionally, the large-signal stability analysis is performed to predict and eliminate the potential parametric oscillations. An experimental prototype with a radio frequency of 900 MHz and an LO frequency of 400 MHz is realized to operate at a supply of 1 V only. By applying an LO power of -4 dBm, the mixer achieves a conversion gain of 12 dB, third-order input intercept point of -11 dBm, single-sideband noise figure of -7 dB, and a power consumption of 12 mW.