Impact of device scaling on the 1/f noise performance of deep submicrometer thin gate oxide CMOS devices

• Published in: Solid-state electronics Vol. 50; no. 7-8; pp. 1219 - 1226
• Main Authors: Chew, Kok Wai, Yeo, Kiat Seng, Chu, Shao-Fu Sanford, Cheng, Michael
• Format: Journal Article
• Language: English
• Published: Oxford Elsevier Ltd 01.07.2006; Elsevier Science
• Subjects: 1/f Noise; Applied sciences; Corner frequency; Design. Technologies. Operation analysis. Testing; Device geometry scaling; Electronics; Exact sciences and technology; Integrated circuits; Lorentzian spectra; Low standby power transistor; Nitridation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Technology scaling; Transistors; Corner frequency; 1/f Noise; Technology scaling; Nitridation; Device geometry scaling; Lorentzian spectra; Low standby power transistor; Performance evaluation; Transistor gate; Nitriding; Transistor; 1/f noise; Aspect ratio; Low voltage; High voltage; Gate oxide; Complementary MOS technology; Miniaturization; Advanced technology; Spectral density; Low-power electronics; Current density; Damaging
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2006.07.004

This paper presents the effects of technology and geometry scaling on the 1/f noise performance of deep submicrometer transistors taken from four advanced CMOS technologies, namely the 0.13μm, 0.18μm, 0.25μm and 0.35μm nodes. For the 0.13μm technology node, three different process flavours consisting of the generic (G) process flow, the low voltage/high performance (LV/HP) process flow and the low standby power (LSP) process flow have been investigated. The higher degree of gate dielectric nitridation with technology downscaling from 0.35μm node to 0.13μm G node has resulted in a severe degradation of the 1/f noise performance of the transistors by approximately three orders of magnitude. On the contrary, the employment of 0.13μm LSP transistors have been demonstrated to lower the 1/f noise spectra by approximately two orders of magnitude as compared to the 0.13μm LV/HP transistors, which gives the worst 1/f noise performance among the three different process flavours in the 0.13μm node. The study of device geometry scaling on 0.13μm LSP transistors shows that in general the scaling trend follows the SId∝WL3 rule, where SId, W and L represent the current noise spectral density, the active gate width and length of the transistor, respectively. For devices with gate area <1μm2, a large dispersion in the 1/f noise level can be seen. This phenomenon has been correlated to the existence of Lorentzian-like spectra for small area transistors. The investigation of the effect of scaling the transistor’s aspect ratio (W/L) reveals a (SId×WL)∝WL2 dependence.