Gate Driver Supply Architectures for Common Mode Conducted EMI Reduction in Series Connection of Multiple Power Devices

• Published in: IEEE transactions on power electronics Vol. 33; no. 12; pp. 10265 - 10276
• Main Authors: Nguyen, Van-Sang, Lefranc, Pierre, Crebier, Jean-Christophe
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE); Institute of Electrical and Electronics Engineers
• Subjects: Architecture; Circuits; Configurations; Driver circuits; Electric power; electromagnetic compatibility; Electromagnetic interference; electromagnetic interference (EMI); Electronic devices; Engineering Sciences; Gate drivers; high-voltage techniques; Noise measurement; Perturbation methods; Power converters; Power supplies; Semiconductor devices; Switching; Transistors; voltage multipliers
• ISSN: 0885-8993; 1941-0107
• DOI: 10.1109/TPEL.2018.2802204

This paper presents a study on the gate driver circuitries that need to be implemented to drive several power devices when associated in series connection. More specifically, the propagation paths of parasitic currents through the gate driver circuitries, exited under high switching speeds, are studied in different configurations trying to minimize common mode currents generated. In a gate driver circuitry for a regular low side-high side switching cell configuration with one upper switch and one lower switch, the voltage transient dv/dt at the middle point applied across the primary-secondary parasitic capacitance of gate driver supplies, and control signal isolation units are the reasons for the generation of conducted electromagnetic interference (EMI) perturbations. In complex power converters, multicell, multilevel, or even series connection of power devices, many driver circuits are required and implemented. Similarly, in such converters, there are several dv/dt sources generated at different floating points producing conducted EMI perturbations from the power part to the control part through many gate driver circuitries. Based on previous works, this paper analyzes the best configuration to minimize parasitic currents, especially reducing the conducted common mode currents in series connected transistors topologies. Simulations and practical results validate the analysis for two power devices in series connection, and then the extrapolations for more power devices in series connection, up to six are discussed and analyzed with the help of simulations results.