VLSI Implementation of H.264 Video Decoder for Mobile Multimedia Application
In this letter, we present a design of a single chip video decoder called advanced mobile video ASIC (A‐MoVa) for mobile multimedia applications. This chip uses a mixed hardware/software architecture to improve both its performance and its flexibility. We designed the chip using a partition between...
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Published in | ETRI journal Vol. 28; no. 4; pp. 525 - 528 |
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Main Authors | , , , , , , , |
Format | Journal Article |
Language | English |
Published |
01.08.2006
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Subjects | |
Online Access | Get full text |
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Summary: | In this letter, we present a design of a single chip video decoder called advanced mobile video ASIC (A‐MoVa) for mobile multimedia applications. This chip uses a mixed hardware/software architecture to improve both its performance and its flexibility. We designed the chip using a partition between the hardware and software blocks, and developed the architecture of an H.264 decoder based on the system‐on‐a‐chip (SoC) platform. This chip contains 290,000 logic gates, 670,000 memory gates, and its size is 7.5 mm×7.5 mm (using 0.25 micron 4‐layers metal CMOS technology). |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 1225-6463 2233-7326 |
DOI: | 10.4218/etrij.06.0206.0009 |