Phase-Delay Cold-FET Pre-Distortion Linearizer for Millimeter-Wave CMOS Power Amplifiers

• Published in: IEEE transactions on microwave theory and techniques Vol. 61; no. 12; pp. 4505 - 4519
• Main Authors: Kao, Kun-Yao, Hsu, Yu-Chung, Chen, Kuan-Wei, Lin, Kun-You
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2013; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplification; CMOS; CMOS integrated circuits; Compressing; Feasibility; Gain; Linearity; Logic gates; Microwaves; millimeter-wave (MMW); monolithic microwave integrated circuit (MMIC); Noise levels; phase-delay linearizer; power amplifier (PA); Power amplifiers; Power generation; pre-distortion; Threshold voltage; Transistors
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2013.2288085

A phase-delay cold-FET pre-distortion linearizer technique is proposed to improve the gain compensation ability compared with the conventional cold-FET pre-distortion linearizer. The gain expansion analysis of the power amplifier (PA) cascading with a pre-distortion linearizer and the comparison with the conventional linearizer and the proposed phase-delay linearizer are provided in this paper. To demonstrate the feasibility of this concept, a single-ended V-band cascode PA with the 90° phase-delay linearizer and a differential K-band common-source PA with the 180° phase-delay linearizer are developed to verify the characteristics. The V-band PA implemented in 90-nm CMOS process exhibits the output 1-dB compression power (OP1 dB) of 13.7 dBm and the power-added efficiency (PAE) at OP1 dB of 14.3%. The K-band PA implemented in 0.18-μm CMOS process demonstrates 17.5-dBm OP1 dB and 13.6% PAE at OP1 dB.