A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC

A 10-bit 200 MS/s pipeline ADC using the capacitor-sharing concept is presented. A charge-neutralization technique is proposed between the 1st and 2nd MDACs to mitigate the memory effect. To further enhance power efficiency, a reference precharge technique is proposed between the 2nd and 3rd MDACs....

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Bibliographic Details
Published inIEEE transactions on circuits and systems. I, Regular papers Vol. 60; no. 11; pp. 2902 - 2910
Main Authors Tseng, Chien-Jian, Hsieh, Yi-Chun, Yang, Ching-Hua, Chen, Hsin-Shu
Format Journal Article
LanguageEnglish
Published New York IEEE 01.11.2013
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Capacitor-sharing
Chips
Circuits
CMOS
Consumption
Conversion
pipeline analog-to-digital converter
Pipelines
Power efficiency
Prototypes
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Summary:A 10-bit 200 MS/s pipeline ADC using the capacitor-sharing concept is presented. A charge-neutralization technique is proposed between the 1st and 2nd MDACs to mitigate the memory effect. To further enhance power efficiency, a reference precharge technique is proposed between the 2nd and 3rd MDACs. The prototype ADC in 90-nm low-power CMOS process exhibits an INL of + 1.59/-1.91 LSB and a DNL of +0.70/-0.75 LSB. Its ENOB is 8.53 bits at input frequency of 2 MHz and 8.05 bits at Nyquist input frequency with the conversion rate of 200 MS/s. It consumes 45.4 mW at 1.2 V supply and occupies an active chip area of 0.53 mm 2 .
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2013.2256212