ERSFQ 8-Bit Parallel Adders as a Process Benchmark

• Published in: IEEE transactions on applied superconductivity Vol. 25; no. 3; pp. 1 - 5
• Main Authors: Kirichenko, Alex F., Vernik, Igor V., Vivalda, John A., Hunt, Rick T., Yohannes, Daniel T.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Benchmark testing; Benchmarking; Circuits; Clocks; Computer architecture; Current measurement; Dissipation; Fabrication; Flux; HPC; Large scale integration; Logic; Power dissipation; RSFQ; Superconductivity; zero static power dissipation; Benchmarking; HPC; RSFQ; zero static power dissipation
• ISSN: 1051-8223; 1558-2515
• DOI: 10.1109/TASC.2014.2371875

We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES's 1.0-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 6-layer 4.5 kA/cm 2 planarized process, and MIT Lincoln Lab's 0.25-μm 4-layer 10 kA/cm 2 process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.