Landing Stencil Code on Godson-T

• Published in: Journal of computer science and technology Vol. 25; no. 4; pp. 886 - 894
• Main Author: 崔慧敏 王蕾 范东睿 冯晓兵
• Format: Journal Article
• Language: English
• Published: Boston Springer US 01.07.2010; Springer Nature B.V
• Subjects: Architects; Architecture; Artificial Intelligence; Chips; Compilers; Computation; Computer architecture; Computer programs; Computer Science; Computers; Data Structures and Information Theory; Design; Designers; Information Systems Applications (incl.Internet); Optimization; Optimization techniques; R&D; Research & development; Short Paper; Software; Software Engineering; Synchronism; Synchronization; Theory of Computation; Tiling; 优化技术; 同步机制; 芯片技术; 计算机系统; 软件架构; many-core; SPM; fine-grain synchronization; compiler; stencil; Jacobi
• ISSN: 1000-9000; 1860-4749
• DOI: 10.1007/s11390-010-9373-6

The advent of multi-core/many-core chip technology offers both an extraordinary opportunity and a profound challenge. In particular, computer architects and system software designers are faced with a unique opportunity to introducing new architecture features as well as adequate compiler technology -- together they may have profound impact. This paper presents a case study （using the 1-D Jacobi computation） of compiler-amendable performance optimization techniques on a many-core architecture Godson-T. Godson-T architecture has several unique features that are chosen for this study： 1） chip-level global addressable memory in particular the scratchpad memories （SPM） local to the processing cores; 2） fine-grain memory based synchronization （e.g., full-empty bit for fine-grain synchronization）. Leveraging state-of-the-art performance optimization methods for 1-D stencil parallelization （e.g., timed tiling and variants）, we developed and implement a number of many-core-based optimization for Godson-T. Our experimental study shows good performance in both execution time speedup and scalability, validate the value of globally accessed SPM and fine-grain synchronization mechanism （full-empty bits） under the Godson-T, and provides some useful guidelines for future compiler technology of many-core chip architectures.