P-Val: Antifuse-Based Package-Level Defense Against Counterfeit ICs

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 35; no. 7; pp. 1067 - 1078
• Main Authors: Basak, Abhishek, Bhunia, Swarup
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Aging; Antifuse; Authentication; Chips; Cloning; Counterfeit; Counterfeit ICs; Counterfeiting; Design; Design engineering; Design modifications; Integrated circuits; Integrity; Package-level; Packages; Pins; Recycling; Semiconductors; Signatures; Validation; integrity; package-level; recycling; counterfeit integrated circuits (ICs); Antifuse (AF); cloning; authentication
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2015.2501311

The rapidly growing incidences of counterfeit integrated circuits (ICs) pose a significant threat to the semiconductor industry. These ICs may suffer from functional, performance, or reliability issues and can affect chip manufacturers, system designers as well as end users. The standard chip/package level structural and functional tests are often inadequate in detecting various forms of counterfeit ICs. Moreover, existing design for security approaches are usually not attractive due to additional design modifications, hardware overhead, test cost, and inadequate robustness. In this paper, we propose a novel, low-overhead package-level IC integrity validation approach, referred to as P-Val, for unified protection against two primary forms of counterfeiting attacks: 1) recycling and 2) cloning. Protection against recycled/remarked chips is achieved through a unique active defense that inserts antifuses (AFs) (one-time programmable) to few select pins inside the package. It effectively disables the functionality or "locks" these pins, which need to be programmed before first-time use to make a chip functional in a system. To protect against cloned ICs, intrinsic random variations in programmed resistances of AFs connected to some of the remaining IC pins are exploited to create unique chip-specific signatures for authentication. P-Val requires no die-level design modifications and remains effective for legacy designs. Moreover, we show that it is effective for small chips with just few pins including analog ICs, where common authentication approaches fail to work. We discuss optimal choice of AF structure and program parameters; their integration in IC packages; and the signature generation/verification process. Through mathematical analysis and simulation results, we demonstrate that the proposed mechanism provides high level of protection against counterfeiting attacks at ultralow overhead (<0.05% package area).