Self-Rectifying Twin-Bit RRAM in 3-D Interweaved Cross-Point Array

• Published in: IEEE journal of the Electron Devices Society Vol. 3; no. 4; pp. 336 - 340
• Main Authors: Chen, Shu-En, Chin, Yung-Wen, Hsieh, Min-Che, Liao, Chu-Feng, Chang, Tzong-Sheng, Lin, Chrong-Jung, King, Ya-Chin
• Format: Journal Article
• Language: English
• Published: IEEE 01.07.2015
• Subjects: Arrays; CMOS integrated circuits; Metals; Microprocessors; System-on-chip; Three-dimensional displays; embedded memory self-rectifying RRAM; nonvolatile memory (NVM); Lateral via resistive RAM (LVRRAM); Back end of line process (BEOL)
• ISSN: 2168-6734; 2168-6734
• DOI: 10.1109/JEDS.2015.2425652

A new self-rectifying twin-bit RRAM in a novel 3-D interweaved cross-point array has been proposed and demonstrated in 28-nm high-k metal gate CMOS back end of line (BEOL) process. This high density of array architecture with the cell size only 70 × 100 × 187 nm can be manufactured without additional mask or process. The RRAM film is formed by via plug over shifting between two metal lines in back-end process with TaN/TaO x N RRAMs on both sides of a single via. The BEOL RRAM shows large read window between states. Fast switching time of 1 us for set operation and 10 us for reset was demonstrated. Excellent selectivity by its asymmetric IV characteristic enables the twin-bit 1R cells to be efficiently stacked in 3-D cross-point arrays without select transistors.