Hardware Implementation on FPGA for Task-Level Parallel Dataflow Execution Engine

• Published in: IEEE transactions on parallel and distributed systems Vol. 27; no. 8; pp. 2303 - 2315
• Main Authors: Wang, Chao, Zhang, Junneng, Li, Xi, Wang, Aili, Zhou, Xuehai
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Computer architecture; dataflow; dependency analysis; Devices; Field programmable gate arrays; Flexibility; FPGA; Hardware; Out of order; parallel architecture; Parallel processing; Platforms; Power efficiency; Programming; Tasks

Heterogeneous multicore platform has been widely used in various areas to achieve both power efficiency and high performance. However, it poses significant challenges to researchers to uncover more coarse-grained task level parallelization. In order to support automatic task parallel execution, this...