Hardware Implementation on FPGA for Task-Level Parallel Dataflow Execution Engine

• Published in: IEEE transactions on parallel and distributed systems Vol. 27; no. 8; pp. 2303 - 2315
• Main Authors: Wang, Chao, Zhang, Junneng, Li, Xi, Wang, Aili, Zhou, Xuehai
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Computer architecture; dataflow; dependency analysis; Devices; Field programmable gate arrays; Flexibility; FPGA; Hardware; Out of order; parallel architecture; Parallel processing; Platforms; Power efficiency; Programming; Tasks
• ISSN: 1045-9219; 1558-2183
• DOI: 10.1109/TPDS.2015.2487346

Heterogeneous multicore platform has been widely used in various areas to achieve both power efficiency and high performance. However, it poses significant challenges to researchers to uncover more coarse-grained task level parallelization. In order to support automatic task parallel execution, this paper proposes a FPGA implementation of a hardware out-of-order scheduler on heterogeneous multicore platform. The scheduler is capable of exploring potential inter-task dependency, leading to a significant acceleration of dependence-aware applications. With the help of renaming scheme, the task dependencies are detected automatically during execution, and then task-level Write-After-Write (WAW) and Write-After-Read (WAR) dependencies can be eliminated dynamically. We extended the instruction level renaming techniques to perform task-level out-of-order execution, and implemented a prototype on a state-of-art Xilinx Virtex-5 FPGA device. Given the reconfigurable characteristic of FPGA, our scheduler supports changing accelerators at runtime to improve the flexibility. Experimental results demonstrate that our scheduler is efficient at both performance and resources usage.