A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 34; no. 8; pp. 1308 - 1319
• Main Authors: Gornik, Andreas, Moradi, Amir, Oehm, Jurgen, Paar, Christof
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: ASIC; Capacitors; circuit-level countermeasure; Circuits; Computer architecture; Cryptography; Decoupling; Design engineering; Discharges (electric); Electronics industry; hardware-based countermeasure; Leakage; Logic; Logic gates; Microprocessors; Power supplies; Power supply; Semiconductors; side-channel analysis; side-channel countermeasure; Transistors; circuit-level countermeasure; Application-specified integrated circuit (ASIC); side-channel analysis; side-channel countermeasure; hardware-based countermeasure
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2015.2423274

Side-channel attacks are one of the major concerns for security-enabled applications as they make use of information leaked by the physical implementation of the underlying cryptographic algorithm. Hence, reducing the side-channel leakage of the circuits realizing the cryptographic primitives is amongst the main goals of circuit designers. In this paper, we present a novel circuit concept, which decouples the main power supply from an internal power supply that is used to drive a single logic gate. The decoupling is done with the help of buffering capacitances integrated into semiconductor. We also introduce-compared to the previously known schemes-an improved decoupling circuit which reduces the crosstalk from the internal to the external power supply. The result of practical side-channel evaluation on a prototype chip fabricated in a 150nm CMOS technology shows a high potential of our proposed technique to reduce the side-channel leakages.