Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis

• Published in: IEEE transactions on electromagnetic compatibility Vol. 52; no. 2; pp. 381 - 391
• Main Authors: Hao-Hsiang Chuang, Wei-Da Guo, Yu-Hsiang Lin, Hsin-Shu Chen, Yi-Chang Lu, Yung-Shou Cheng, Ming-Zhang Hong, Chun-Huang Yu, Wen-Chang Cheng, Yen-Ping Chou, Chuan-Jen Chang, Ku, Joseph, Tzong-Lin Wu, Ruey-Beei Wu
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitance; Data buses; Discontinuity; Double-data-rate synchronous dynamic RAM (DDR SDRAM); eye diagram; High speed; Impedance; Integrated circuit modeling; Integrity; Mathematical models; model extraction; Modules; Packages; Polyimide resins; power distribution network (PDN); power integrity (PI); signal integrity (SI); Silicon; Strategy; Topology; Transmission line measurements
• ISSN: 0018-9375; 1558-187X
• DOI: 10.1109/TEMC.2010.2043108

Under the platform of a high-speed double-data-rate three (DDR3) memory module, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity (SI/PI). For SI part, accurate modeling strategies for signal channels are verified by experiments on samples of address lines. The following what-if analyses of eye diagrams help to identify the discontinuities of package trace to be the bottlenecks and have great effects on the eye diagrams. For PI issues, the modeling methodologies for power distribution networks of data buses are demonstrated and validated with the results of measurement. The analysis indicates that the parasitic effects of the low-cost package structure are the most critical, depicting the importance of improved package design in the next-generation DDR memory modules.