A Parallel Simulation Technique for Multicore Embedded Systems and Its Performance Analysis

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 31; no. 1; pp. 121 - 131
• Main Authors: Yun, Dukyoung, Kim, Sungchan, Ha, Soonhoi
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2012; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accuracy; Analytical models; Backplanes; Computational modeling; Computer simulation; Distributed simulation; embedded system; Embedded systems; Integrated circuit modeling; Messages; Microprocessors; multiprocessor; Optimization; parallel simulation; Running; Simulators; Studies; Synchronization; Time synchronization
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2011.2167329

A virtual prototyping system is constructed by replacing real processing components with component simulators running concurrently. The performance of such a distributed simulation decreases drastically as the number of component simulators increases. Thus, we propose a novel parallel simulation technique to boost up the simulation speed. In the proposed technique, a simulator wrapper performs time synchronization with the simulation backplane on behalf of the associated component simulator itself. Component simulators send null messages periodically to the backplane to enable parallel simulation without any causality problems. Since excessive communication may degrade the simulation performance, we also propose a novel performance analysis technique to determine an optimal period of null message transfer, considering both the characteristics of a target application and the configurations of the simulation host. Through intensive experiments, we show that the proposed parallel simulation achieves almost linear speedup to the number of processor cores if the frequency of null message transfer is optimally decided. The proposed analysis technique could predict the simulation performance with more than 90% accuracy in the worst case for various target applications and simulation environments we have used for experiments.