A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application

• Published in: IEEE journal of solid-state circuits Vol. 46; no. 7; pp. 1596 - 1605
• Main Authors: Hongtao Xu, Palaskas, Y., Ravi, A., Sajadieh, M., El-Tanani, M. A., Soumyanath, K.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2011; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplifiers; class-D; CMOS; CMOS integrated circuits; CMOS PA; Driver circuits; Drivers; Efficiency; Integrated circuits; Linearity; Mathematical analysis; OFDM; Outphasing; power amplifier; Power amplifiers; Power generation; Radio frequency; SOC; Switches; Transformers; Transistors; Wireless communication; WLAN
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2011.2143930

A 2.4 GHz outphasing power amplifier (PA) is implemented in a 32 nm CMOS process. An inverter-based class-D PA topology is utilized to obtain low output impedance and good linearity in the outphasing system. MOS switch non-idealities, such as finite on-resistance and finite rise and fall times are analyzed for their impact on outphasing linearity and efficiency. Outphasing combining is performed via a transformer configured to achieve reduced loss at power backoff. The fabricated class-D outphasing PA delivers 25.3 dBm peak CW power with 35% total system Power Added Efficiency (includes all drivers). Average OFDM power is 19.6 dBm with efficiency 21.8% when transmitting WiFi signals with no linearization required. The PA is packaged in a flip-chip BGA package. Good linearity performance (ACPR and EVM) demonstrates the applicability of inverter-based class-D amplifiers for outphasing configurations.