Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 27; no. 11; pp. 2088 - 2092
• Main Authors: Kim, Hyunjin, Hong, Hyejeong, Kim, Hong-Sik, Ahn, Jin-Ho, Kang, Sungho
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Dynamic voltage scaling; Dynamic voltage scaling (DVS); Dynamics; Electric potential; Energy consumption; Energy efficiency; Energy use; energy-aware systems; Frequency; Iterative algorithms; load balancing and task assignment; on-chip multiprocessor; power management; Processor scheduling; Reliability engineering; Schedules; Scheduling algorithm; Shutdowns; System-on-a-chip; Tasks; Voltage; Voltage control
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2008.2006094

This paper proposes an algorithm that provides both dynamic voltage scaling and power shutdown to minimize the total energy consumption of an application executed on an on-chip multiprocessor. The proposed algorithm provides an extended schedule and stretch method, where task computations are iteratively stretched within the slack of a time-constrained dependent task set. In addition, the break-even threshold interval for amortizing the shutdown overhead is considered. By evaluating each set of stretched task computations, an energy-efficient set is obtained. The proposed dynamic voltage scaling efficiency metric is the ratio of the reduced energy to the increased cycle time when the supply voltage is scaled, which can be used to determine the task computation cycle to be stretched. Experimental results show that the proposed algorithm outperforms the traditional schedule and stretch method in the various evaluations of target real applications.