Design and Development of Multi-Die Laterally Placed and Vertically Stacked Embedded Micro-Wafer-Level Packages

• Published in: IEEE transactions on components, packaging, and manufacturing technology (2011) Vol. 1; no. 1; pp. 52 - 59
• Main Authors: Sharma, G, Rao, V S, Kumar, A, Lim Ying Ying, Khong Chee Houe, Lim, S, Sekhar, V N, Rajoo, R, Kripesh, V, Lau, J H
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.01.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Compounds; Copper; Design. Technologies. Operation analysis. Testing; Die stacking; Dielectric, amorphous and glass solid devices; Dielectrics; Electronics; embedded wafer package; Exact sciences and technology; Fabrication; Integrated circuits; Magnetic devices; multi-die; Packaging; Reliability; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Stacking; Studies; Thermal cycling; thin film passives; Thin films; Stacking; Thermal cycle; Driver; Inductor; Thin film; Integrated circuit bonding; multi-die; Three dimensional structure; thin film passives; Electronic packaging; Silicon; Wafer; Die; Q factor; Multichip module; Wafer-level packaging; Accelerated test; embedded wafer package; Die stacking; Humidity effect; Solder bump; Soldered joint; Miniaturization; Reliability; Capacitor
• ISSN: 2156-3950; 2156-3985
• DOI: 10.1109/TCPMT.2010.2101470

Two embedded micro-wafer-level packages (EMWLP) with 1) laterally placed and 2) vertically stacked thin dies are designed and developed. Three-dimensional stacking of thin dies is demonstrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10 mm × 10 mm × 0.4 mm and solder ball pitch of 0.4 mm. As part of the development several key processes like thin die stacking, 8-in wafer encapsulation using compression molding, low-temperature dielectric with processing temperature less than 200°C have been developed. The EMWLP components success fully pass 1000 air to air thermal cycling (-40°C to 125°C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (>; 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q-factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL, and package thicknesses can lead to designs with improved mechanical reliability.