TABS: Temperature-Aware Layout-Driven Behavioral Synthesis

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 18; no. 12; pp. 1649 - 1659
• Main Authors: Krishnan, V, Katkoori, S
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.12.2010; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Applied sciences; Behavioral synthesis; Circuit simulation; Circuit synthesis; Cooling; Costs; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronics; Energy consumption; Exact sciences and technology; High level synthesis; high-level synthesis (HLS); Integrated circuits; multistage simulated annealing; on-chip temperature variations; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Simulated annealing; Studies; Temperature; Temperature distribution; Theoretical study. Circuits analysis and design; thermal hot spots; Thermal management; Very large scale integration; Performance evaluation; multistage simulated annealing; Circuit design; Thermal management (packaging); high-level synthesis (HLS); Temperature effect; High temperature; Behavioral analysis; on-chip temperature variations; Simulated annealing; Electric power consumption; System synthesis; High level synthesis; thermal management; Multistage circuit; Computer aided design; Temperature distribution; VLSI circuit; Thermal behavior; Scheduling; thermal hot spots; Algorithm; Behavioral synthesis; Integrated circuit layout; Cooling system; Circuit synthesis; Low-power electronics; Reliability
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2009.2026047

With rising power densities in modern VLSI circuits, thermal effects are becoming important in the design of ICs. Elevated chip temperatures have an adverse impact on performance, reliability, power consumption, and cooling costs. To ensure adequate thermal management, all phases of the design flow must account for thermal effects on their design decisions. We present a two-stage simulated annealing-based high-level synthesis technique that combines power minimization with temperature-aware scheduling, binding, and floorplanning. In our technique, the first stage of the simulated annealing algorithm creates a low-power solution, which is then iteratively improved by the second stage to minimize estimated on-chip peak temperature using accurate module-level temperature estimation. We show that minimizing average power alone does not guarantee minimal peak temperatures. However, our approach consistently finds solutions that have lower on-chip peak temperatures and uniform on-chip temperature distributions, compared to a traditional low-power synthesis methodology that minimizes average power. Experiments show that our method reduces peak temperatures on average by 12% and up to 16%, compared to a traditional low-power synthesis algorithm that minimizes average power. These improvements in chip-level temperature distributions are achieved with a modest increase in chip area of under 15% on average.