Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High- \kappa Gate Dielectrics

• Published in: IEEE transactions on electron devices Vol. 56; no. 1; pp. 100 - 108
• Main Authors: Schlosser, M., Bhuwalka, K.K., Sauter, M., Zilbauer, T., Sulima, T., Eisele, I.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.01.2009; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; CMOS; Design. Technologies. Operation analysis. Testing; Devices; Dielectrics; Drain current; Electric fields; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; FETs; Gates; high- kappa; Integrated circuits; inverter delay; Logic gates; metal-oxide-semiconductor field-effect transistor (MOSFET); MOSFETs; Permittivity; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; subthreshold slope; Transistors; tunnel FET; Tunneling; Tunnels (transportation); subthreshold slope; Drain current; tunnel FET; high- kappa; inverter delay; metal-oxide-semiconductor field-effect transistor (MOSFET); Inverter; MOSFET; metal- oxide-semiconductor field-effect transistor (MOSFET); Performance characteristic; Tunnel effect; Tunnel transistors; Prospective; Field effect transistor; high-K; Induced current; Complementary MOS technology; High k dielectric; Delay time; Permittivity

The tunnel field-effect transistor (tunnel FET) is a promising candidate for future CMOS technology. Its device characteristics have been subject to a variety of experimental and theoretical studies. In this paper, we evaluate the influence of using a high-kappa gate dielectric in the tunnel FET com...