Real-Time Simulation of Power Electronic Systems Based on Predictive Behavior

• Published in: IEEE transactions on industrial electronics (1982) Vol. 67; no. 9; pp. 8044 - 8053
• Main Authors: Liu, Chen, Bai, Hao, Zhuo, Shengrong, Zhang, Xinyue, Ma, Rui, Gao, Fei
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE); Institute of Electrical and Electronics Engineers
• Subjects: Automatic; Circuits; Computational modeling; Computer simulation; Electric power; Electronic systems; Engineering Sciences; Field programmable gate arrays; Field-programmable gate array (FPGA); Fluid mechanics; hardware-in-the-loop (HiL); Hardware-in-the-loop simulation; Insulated gate bipolar transistors; Integrated circuit modeling; Mathematical model; Mechanics; Parallel processing; parallel structure; Physics; Power converters; power electronic system modeling; Real time; real-time simulation; Real-time systems; Semiconductor devices; Simulation; Switching circuits; Thermics; Topology
• ISSN: 0278-0046; 1557-9948
• DOI: 10.1109/TIE.2019.2941135

The field-programmable gate array (FPGA) based hardware-in-the-loop (HiL) test, which minimizes the time-step of the real-time simulation below 500 ns, is an enabling technology for the development of the control unit of high-power electronic systems (HPE). In order to improve the time performance of FPGA-based HiL, this article proposes a novel parallel structure using the predictive behavior of the power electronic system. With this structure, we design an improved system-level solver applied to HPE. A piecewise insulated-gate bipolar transistor (IGBT) model is used to determine the state of the switch, offering a quasi-realistic model of the power converter. A parallel integration method is also implemented to solve the status of the circuit elements. Moreover, the proposed parallel structural can execute both the IGBT model and circuit element model at the same time, thus, reducing the simulation time-step significantly. The numerical accuracy of the solution, the architecture design, and the issue of the parallel computation are discussed in detail. An ac-dc-ac topology is presented as a case study. At last, a 25 ns time step in the National Instruments FlexRIO platform is achieved. Results comparison with the reference model is also identified and discussed.