Minimum-Period Register Binding

This paper points out that register binding in the high-level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions often lead to different smallest feasible clock periods. Based on that observation, we formally draw...

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Bibliographic Details
Published inIEEE transactions on computer-aided design of integrated circuits and systems Vol. 28; no. 8; pp. 1265 - 1269
Main Authors Huang, Shih-Hsu, Cheng, Chun-Hua
Format Journal Article
LanguageEnglish
Published New York IEEE 01.08.2009
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Benchmarking
Binding
Circuit synthesis
Circuits
Clocks
Computer aided design
Design engineering
High level synthesis
Logic circuits
Minimization
Optimization
performance optimization
Polynomials
Registers
resource binding
Resource management
sequential synthesis
Timing
timing optimization
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Summary:This paper points out that register binding in the high-level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions often lead to different smallest feasible clock periods. Based on that observation, we formally draw up the problem of register binding for clock-period minimization. Compared with the left edge algorithm, experimental data show that, in most benchmark circuits, our approach can greatly reduce the clock period without any overhead on the number of registers.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2009.2021009