Investigation of Human-Body-Model and Machine-Model ESD Robustness on Stacked Low-Voltage Field-Oxide Devices for High-Voltage Applications

• Published in: IEEE transactions on electron devices Vol. 63; no. 8; pp. 3193 - 3198
• Main Authors: Huang, Yi-Jie, Ker, Ming-Dou
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Current measurement; Damping; Damping effect; Devices; Electronics industry; electrostatic discharge (ESD) protection; Electrostatic discharges; high-voltage (HV) ICs; human body model (HBM); Insulators; Latch-up; machine model (MM); Resistance; Robustness; Silicon; Stacking; Static electricity; Transient analysis; Waveforms
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2016.2583380

Electrostatic discharge (ESD) robustness of lowvoltage (LV) field-oxide devices in stacked configuration for highvoltage (HV) applications was investigated in a 0.5-μm HV silicon on insulator (SOI) process. Stacked LV field-oxide devices with different stacking numbers have been verified in a silicon chip to exhibit both a high ESD robustness and latch-up immunity for HV applications. The effect of turn-on resistance in the stacked ESD protection device on ESD current waveform under human body model (HBM) and machine model (MM) ESD tests was studied. The resistance of stacked device has a significant impact on the ESD peak current and damping waveform, especially in MM ESD test. The MM ESD level can be increased by the numbers of LV field-oxide devices in stacked configuration, but the HBM ESD level is still kept the same. The mechanism to cause such a result has been theoretically analyzed in detail in this paper.