Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 28; no. 9; pp. 1373 - 1386
• Main Authors: Pathak, M., Sung Kyu Lim
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2009; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Constraint optimization; Construction; Costs; Delay; Integer linear programming; Integrated circuits; Linear programming; Minimization; Optimization; Relocation; Routing; Stacking; Steiner routing; Steiner trees; Studies; thermal optimization; three-dimensional (3-D) integrated circuit (IC); Through-silicon vias; through-silicon-via (TSV); Topology; Trees
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2009.2024707

In this paper, we present a performance and thermal-aware Steiner routing algorithm for three-dimensional (3-D) stacked integrated circuits. Our algorithm consists of two steps: tree construction and tree refinement. Our tree construction algorithm builds a delay-oriented Steiner tree under a given thermal profile. We show that our 3-D tree construction involves minimization of two-variable Elmore delay function. In our tree refinement algorithm, we reposition the through-silicon-vias (TSVs) used in existing Steiner trees while preserving the original routing topology for further thermal optimization under a performance constraint. We employ a novel scheme to relax the initial nonlinear programming formulation to integer linear programming and consider all TSVs from all nets simultaneously. Our tree construction algorithm outperforms the popular 3-D maze routing by 52% in terms of performance at the cost of 15% wirelength and 6% TSV count increase for four-die stacking. In addition, our TSV relocation results in 9% maximum-temperature reduction at no additional area cost. We also provide extensive experimental results, including the following: (1) the wirelength and delay distribution of various types of 3-D interconnects; (2) the impact of TSV RC parasitics on routing and TSV relocation; and (3) the impact of various bonding styles on routing and TSV relocation. Last, we provide results on two-die stacking.