A Hybrid RF/Baseband Precoding Processor Based on Parallel-Index-Selection Matrix-Inversion-Bypass Simultaneous Orthogonal Matching Pursuit for Millimeter Wave MIMO Systems

• Published in: IEEE transactions on signal processing Vol. 63; no. 2; pp. 305 - 317
• Main Authors: Lee, Yun-Yueh, Wang, Ching-Hung, Huang, Yuan-Hao
• Format: Journal Article
• Language: English
• Published: New York IEEE 15.01.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Antenna arrays; Baseband; beamforming; Data transmission; Design engineering; digital signal processing chips; Hardware; Integrated circuits; Microprocessors; millimeter wave communication; Millimeter waves; MIMO; phased arrays; precoding; Radio frequencies; Radio frequency; Receiving antennas; Reconstruction; Reconstruction algorithms; Vectors
• ISSN: 1053-587X; 1941-0476
• DOI: 10.1109/TSP.2014.2370947

A millimeter wave (mm-wave) communication system provides multi-Gb/s data rates in short-distance transmission. Because millimeter waves have short wavelength, transceivers can be composed of large antenna arrays to alleviate severe signal attenuation. Furthermore, the link performance can be improved by adopting precoding technology in multiple data stream transmission. However, the complexity of radio frequency (RF) chains increases when large antenna arrays are used in mm-wave systems. To reduce the hardware cost, the precoding circuit can be jointly designed in both analog and digital domains to reduce the required number of RF chains. This paper proposes a new method of building the joint RF and baseband precoder that reduces the computation complexity of the original precoder reconstruction algorithm and enables highly parallel hardware architecture. Moreover, the proposed precoder reconstruction algorithm was designed and implemented using TSMC 90-nm UTM CMOS technology. The proposed precoder reconstruction processor supports the transmissions of one to four data streams for 8 × 8 mm-wave multiple-input multiple-output systems. The operating frequency of this chip was 167 MHz, and the power consumption was 243.2 mW when the supply voltage was 1 V. The core area of the postlayout result was about 3.94 mm 2 . The proposed processor achieved 4, 4.9, 6.7, and 6.7 M channel matrices per second in four-, three-, two-, and one-stream modes, respectively.