Modeling Asymmetric Operation in Double-Gate Junctionless FETs by Means of Symmetric Devices

This paper aims to model asymmetric operation in double-gate junctionless FETs. Following a rigorous approach, we find that asymmetric operation can be simulated by combining two symmetric junctionless FETs, what we call the virtual symmetric device concept. In addition to the benefits in terms of c...

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Bibliographic Details
Published inIEEE transactions on electron devices Vol. 61; no. 12; pp. 3962 - 3970
Main Authors Jazaeri, Farzan, Barbut, Lucian, Sallese, Jean-Michel
Format Journal Article
LanguageEnglish
Published New York IEEE 01.12.2014
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Accumulation
Analytical models
asymmetric
compact model
double gate (DG)
Electric potential
FET
Field effect transistors
junctionless (JL)
Logic gates
Mathematical model
nanowire
compact model
FET
junctionless (JL)
asymmetric
Accumulation
double gate (DG)
nanowire
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Summary:This paper aims to model asymmetric operation in double-gate junctionless FETs. Following a rigorous approach, we find that asymmetric operation can be simulated by combining two symmetric junctionless FETs, what we call the virtual symmetric device concept. In addition to the benefits in terms of compactness and coherence, such equivalence is used to develop a complete charge-based model for independent double-gate junctionless architectures, including mismatch in gate capacitance and material work functions.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2014.2361358