A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 46; no. 7; pp. 1575 - 1584
• Main Authors: Sundstrom, T., Svensson, C., Alvandpour, A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2011; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog-to-digital converter (ADC); Circuits; Clocks; CMOS; CMOS analog integrated circuits; current-mode; data converter; foreground digital calibration; Gain; High speed; Low frequencies; low power; MOS devices; Noise levels; pipeline; Pipelines; Redundancy; Sampling; Settling; Timing; Transistors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2011.2143811

This paper presents a high-speed single-channel pipeline analog-to-digital converter sampling at 2.4 GS/s. The high sample rate is achieved through the use of fast open-loop current-mode amplifiers and the early comparison scheme. The bounds on the sub-ADC sampling instance are analyzed based on sufficient settling for a decision as well as metastability. Implemented in a 65 nm general purpose CMOS technology the SNDR is above 30.1 dB in the Nyquist band, being 34.1 and 31.3 dB at low frequency and Nyquist, respectively. This shows that multi-GS/s pipeline ADCs are feasible as key building blocks in interleaved structures.