Improving the specific on-resistance and short-circuit ruggedness tradeoff of 1.2-kV-class SBD-embedded SiC MOSFETs through cell pitch reduction and internal resistance optimization

• Published in: 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD) pp. 227 - 230
• Main Authors: Kono, Hiroshi, Asaba, Shunsuke, Ohashi, Teruyuki, Ogata, Takahiro, Furukawa, Masaru, Sano, Kenya, Yamaguchi, Masakazu, Suzuki, Hisashi
• Format: Conference Proceeding
• Language: English
• Published: The Institute of Electrical Engineering of Japan 30.05.2021
• Subjects: MOSFET; Resistance; SBD-embedded MOSFET; Schottky barriers; Schottky diodes; Short-circuit withstand time; SiC MOSFET; Silicon carbide; Switches; Switching loss
• ISSN: 1946-0201
• DOI: 10.23919/ISPSD50666.2021.9452314

The impact of cell size and JFET width reduction on static and dynamic device characteristics is investigated in 1.2-kV-class Schottky barrier diode (SBD)-embedded SiC metal-oxide-semiconductor field effect transistors (MOSFETs). We compare a conventional SBD-embedded MOSFET with improved SBD-embedded MOSFETs with smaller cell pitch and JFET width than the conventional SBD-embedded SiC MOSFET. The optimized SBD-embedded SiC MOSFETs achieve 39% lower on-resistance and 16% lower switching energy loss compared with the conventional design. We also investigate the tradeoff between R on A and short-circuit withstand time (t SC ). Although R on A reduction generally causes a decrease in short circuit withstand capability and reverse conduction capability, we demonstrate that the optimized SBD-embedded SiC MOSFETs have a lower forward voltage drop and short circuit withstand capability. These results show that it is possible to simultaneously reduce R on A and improve t SC with adequate optimization.