Analyses of thermal stresses and control schemes for fast temperature ramps of batch furnaces [IC manufacture]

• Published in: IEEE transactions on semiconductor manufacturing Vol. 10; no. 4; pp. 433 - 437
• Main Authors: FAN, Y.-H, QIU, T
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.1997; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Cooling; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Furnaces; Integrated circuits; Microelectronic fabrication (materials and surfaces technology); Predictive models; Semiconductor device modeling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Stress control; Temperature control; Temperature distribution; Thermal stresses; Thermoelasticity; Thermal stress; Temperature distribution; Heat treatment; Integrated circuit; Temperature control; Batch furnace; Modeling
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/66.641485

This work studies fast temperature ramps of batch furnaces under different control schemes based on thermal and stress analyses. A thermal model is first developed to predict temperature distributions on silicon wafers during ramping processes. Thermoelastic model of stresses is then used to predict the onset of slip-line generation under dynamic conditions. Three control schemes, one based on a maximum allowable within-wafer temperature difference, one with a constant cooling rate, and the third based on the condition for onset of slip generation, are then analyzed. The results show that in order to achieve the highest ramp rates while maintaining defect-free wafer processing, the ultimate criterion for temperature control of the furnaces should be the condition for the onset of defect generation instead of the conventional scheme based on constant ramp rates.