DC-Link Voltage Stabilization for Reduced DC-Link Capacitor Inverter

• Published in: IEEE transactions on industry applications Vol. 50; no. 1; pp. 404 - 414
• Main Authors: Lee, Wook-Jin, Sul, Seung-Ki
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Active damping; Capacitors; constant power load (CPL); Damping; dc-link capacitor; dc-link voltage stabilization; Electric potential; electrolytic capacitor; Electrolytic capacitors; Equations; Inverters; Mathematical model; Motors; Pulse duration modulation; pulsewidth modulation (PWM) inverters; Stabilization; Vectors; Voltage; Voltage control
• ISSN: 0093-9994; 1939-9367
• DOI: 10.1109/TIA.2013.2268733

In conventional motor drive systems using pulsewidth modulation (PWM) inverters, large electrolytic capacitors are used for stabilization of the dc-link voltage. Since the electrolytic capacitors are bulky and reduce reliability of the system due to short lifetime, there have been many efforts to eliminate or reduce the electrolytic capacitors in the motor drive system. However, the PWM inverter with reduced dc-link capacitor has a problem that the dc-link voltage is less stable compared to the conventional inverter because the capability of storing energy is also reduced. In this paper, a dc-link voltage stabilization algorithm using an active damping is proposed so that the dc-link voltage can be stabilized with reduced dc-link capacitor. To achieve load-/source-independent stabilization, a source state estimator which estimates both source voltage and current is also proposed. The fluctuation of the dc-link voltage due to a step load change can be also suppressed under the tolerance range using the estimated source current. The effectiveness of the proposed methods is evaluated by experimental results.