Ultralow Capacitance Transient Voltage Suppressor Design

• Published in: IEEE transactions on electron devices Vol. 63; no. 8; pp. 3064 - 3068
• Main Authors: Lo, Kuo-Hsuan, Huang, Chien-Hao, Weng, Wu-Te, Huang, Tsung-Yi, Su, Hung-Der, Gong, Jeng, Huang, Chih-Fang
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bipolar-CMOS-DMOS (BCD); Capacitance; Clamps; Devices; Diodes; Discharges (electric); Doping; Electric potential; electrostatic discharge (ESD); Electrostatic discharges; High speed; IEC; Junctions; low capacitance; Suppressors; Testing; transient voltage suppressor (TVS); Voltage
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2016.2582320

A novel transient voltage suppressor (TVS) that features ultralow capacitance is proposed. This structure is able to reduce the input capacitance by 21.1%, and is designed to protect against electrostatic discharge (ESD) issues for highspeed ports. The device is also able to withstand IEC 61000-4-2 contact testing at ±14 kV and transmission line pulse (TLP) testing at 20 A. The device is fabricated using a typical planar Bipolar-CMOS-DMOS (BCD) process. By slotting the doping well to decrease the concentration of diodes, a TVS with an ultralow C j is obtained without the need to add to the process procedures or without damaging the ESD capability.