Pulsed-Latch Aware Placement for Timing-Integrity Optimization

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 30; no. 12; pp. 1856 - 1869
• Main Authors: Chuang, Yi-Lin, Kim, Sangmin, Shin, Youngsoo, Chang, Yao-Wen
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2011; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Circuit design; Circuit synthesis; Flip-flops; Generators; Insertion; Integrity; Latches; Optimization; Physical design; Placement; Pulse generation; Pulse generators; pulsed-latch; Studies; Time measurements; Timing
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2011.2165717

Utilizing pulsed-latches in circuit designs is one emerging solution to timing improvements. Pulsed-latches, driven by a brief clock signal generated from pulse generators, possess superior design parameters over flip-flops. If the pulse generator and pulsed-latches are not placed properly, however, pulse-width degradations at pulsed-latches and thus timing violations might occur. In this paper, we present a unified placement framework for pulsed-latches to maintain the timing integrity. Our new placer has the following distinguished features: 1) a multilevel analytical placement framework to effectively prevent the potential pulse-width distortion problem; 2) a physical-location aware pulse-generator insertion algorithm to identify each desired group of a pulse generator and latches; and 3) a new optimization gradient for global placement to consider the impact of load capacitance of generators. Experimental results show that our placement flow can effectively consider pulse-width integrity and thus achieve much smaller total/worst negative slacks with marginal wirelength overheads, compared to a leading commercial and an academic placement flows.