Termination Sequence Generation Circuits for Low-Density Parity-Check Convolutional Codes

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 53; no. 9; pp. 1909 - 1917
• Main Authors: Bates, S., Elliott, D.G., Swamy, R.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Application specific integrated circuits; Blocking; Circuits; Coding and decoding; Communication standards; Complement; Convolutional codes; data communication; Decoding; Encoders; Error correction codes; Field programmable gate arrays; Linear algebra; Networks; Packet switching; Parity check codes; Streaming media; Voice
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2006.880313

Low-density parity-check convolutional codes (LDPC-CCs) complement their popular block-oriented counterparts and may be more suitable in certain communication applications. These include streaming voice, video, and packet switching networks. In order to use these codes efficiently we must generate termination sequences similar to those used in conventional convolutional codes. In this paper, we present a construction method for termination sequence generation circuits suitable for field-programmable gate arrays and application-specific integrated circuits. This method uses linear algebra to determine the termination sequence for a small number of states of the encoder and converts these solutions into a sequential circuit. Results are presented for several realizations of termination circuits for a (128,3,6) LDPC-CC