A QFHD 30-frames/s HEVC Decoder Design

• Published in: IEEE transactions on circuits and systems for video technology Vol. 26; no. 4; pp. 724 - 735
• Main Authors: Chiang, Pai-Tse, Ting, Yi-Ching, Chen, Hsuan-Ku, Jou, Shiau-Yu, Chen, I-Wen, Fang, Hang-Chiu, Chang, Tian-Sheuan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bandwidth; Buffer storage; Buffers; CMOS; Coding; Computation; Computer architecture; Computer memory; Context; decoder; Decoding; High efficiency video coding; Logic circuits; Motion compensation; Pipelines; Transforms; Video compression; VLSI implementation; Decoder; High Efficiency Video Coding (HEVC); very-large-scale integration (VLSI) implementation
• ISSN: 1051-8215; 1558-2205
• DOI: 10.1109/TCSVT.2015.2409019

The High Efficiency Video Coding (HEVC) standard provides superior compression with large and variablesize coding units and advanced prediction modes, which leads to high buffer costs, memory bandwidth, and irregular computation for ultra high-definition video decoding hardware. Thus, this paper presents an HEVC decoder with a four-stage mixed block size pipeline to reduce the pipeline stage buffer size by approximately 91% compared with the 64×64 block-based pipeline. The high memory bandwidth due to motion compensation problem was solved by 16 × 16 block-based data access, precision-based data access, and a smart buffer to reduce the data bandwidth by 88%. In addition, for irregular computation, a reconfigurable architecture was adopted to unify the variable-size transform. A common intra-prediction module was also designed with a 4 × 4 block-based bottom-up computation for variable-size intra prediction and modes in a regular manner. Furthermore, the corner position computation for the motion vector predictor was applied to handle variable-size motion compensation. Finally, the implementation with the TSMC 90-nm CMOS process used 467k logic gates and 15.778 kB of on-chip memory and supported 4096×2160 at 30-frames/s video decoding at a 270-MHz operation frequency.