Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures
This paper addresses the automated synthesis of a custom network-on-chip architecture whose topology is optimized for the specific communication requirements of the target device. The optimization objectives include power consumption and resource usage. This paper presents a two-stage synthesis appr...
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Published in | IEEE transactions on computer-aided design of integrated circuits and systems Vol. 27; no. 8; pp. 1425 - 1438 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
New York
IEEE
01.08.2008
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | This paper addresses the automated synthesis of a custom network-on-chip architecture whose topology is optimized for the specific communication requirements of the target device. The optimization objectives include power consumption and resource usage. This paper presents a two-stage synthesis approach consisting of the following: (1) core to router mapping and (2) custom topology and route generation. In particular, it presents an optimal technique for core to router mapping [stage (1)] and a factor-2 approximation algorithm for custom topology generation [stage (2)]. The superior quality of the techniques is established by experimentation with benchmark applications and by comparisons with existing approaches. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0278-0070 1937-4151 |
DOI: | 10.1109/TCAD.2008.925775 |