PART: Programmable Array Testing Based on a Partitioning Algorithm

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 3; no. 2; pp. 142 - 149
• Main Authors: Somenzi, F., Silvano Gai, Mezzalama, M., Prinetto, P.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.04.1984; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Design automation; Electronics; Equations; Exact sciences and technology; Integrated circuits; Partitioning algorithms; Power generation; Programmable logic arrays; Research and development; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; System testing; Test pattern generators; Very large scale integration; Circuit design; Test; Algorithm; Integrated circuit; Defect detection
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.1984.1270068

PART is a system for PLA testing and design verification, intended to be properly interfaced with other existing tools to generate a comprehensive design environment. To this purpose, it provides several facilities, among which the capability of generating a fault population on the basis of layout information. PART aims at producing a very compact test set for all detectable crosspoint defects, using limited amounts of run time and storage. This is achieved by means of an efficient partitioning algorithm together with powerful heuristics. Test minimality is ensured by a simple procedure. In the present paper these are discussed, experimental results are given and a comparison with competing strategies is made.