Efficient Adaptive Multi-Level Privilege Partitioning With RTrustSoC

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 72; no. 2; pp. 497 - 509
• Main Authors: Milan, Raphaele, Bossuet, Lilian, Lagadec, Loic, Andres Lara-Nino, Carlos, Colombier, Brice, Bollengier, Theotime
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2025; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Computer architecture; Computer Science; Cryptography and Security; Cybersecurity; Hardware; hardware IP core protection; hardware security; Logic; Microprocessors; Partitioning; Program processors; Protection; Reconfiguration; secure architecture; Secure system-on-chip; Security; Software; Hardware IP core protection; Secure system-on-chip; Hardware security; Secure architecture
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2024.3413364

In recent years, heterogeneous SoCs-comprised of multiple processor cores and programmable logic-have greatly progressed both complexity and performance. From a security point of view, this leads to an expansion of the attack surface exposed to adversaries. To address this issue, in this article, we propose a novel heterogeneous SoC architecture called RTrustSoC. Our proposal includes an innovative fully-reconfigurable post-deployment strategy for partitioning the SoC architecture into multiple exclusion levels-worlds-with customizable degrees of privilege. We aim to provide SoC designers with fine control over the security of the system by segregating trusted hardware components from third-party IPs with "on-demand" hardware isolation. Therefore, we expect that an RTrustSoC instance could evolve from a multi-world SoC to a fully trusted platform as IPs progressively develop. RTrustSoC also proposes a dynamic reconfigurable penalty system to monitor the third-party IPs and take measures in case of a detected abnormal behavior. Our experimental testing on an AMD-Xilinx Zynq-7000 SoC-FPGA showed the penalty of the proposed isolation strategy to be small, up to 1% in LUT and 0.7% Flip Flop utilization, thus enabling to an efficient security solution. RTrustSoC introduces a novel design paradigm, evolving from the binary notion of security-trusted vs untrusted-into a flexible set of worlds that can be adapted to any scenario. We demonstrate a real case scenario of RTrustSoC use on time-based cache memory attacks with implementation results.